CODE | VLSI Style Tasks |
---|---|
16V01 | High-speed and energy-efficient have skip adder working under a broad variety of source voltage levels |
16V02 | Design of reduced power, higher efficiency 2-4 and 4-16 mixed-logic range decoders |
16V03 | Design of higher velocity multiplier using modified presentation area criteria with hybrid have look-ahead adder |
16V04 | Design of reversible 32-little bit BCD add-subtract device using parallel pipelined method |
16V05 | Design of high acceleration multiplier making use of modified booth algorithm with cross carry look-ahead adder |
15V26 | Aging-Aware Reliable Multiplier Design With Adaptive Keep Logic |
15V27 | Style and Analysis of Approximate Compressors for Multiplication |
15V28 | Recursive Strategy to the Design of a Parallel Self-Timed Adder |
15V29 | High-speed and energy-efficient have miss out adder working under a broad range of source voltage levels |
15V30 | High-Speed, Modified, Mass stimulated, Ultra-Low-Voltage, Domino Inverter |
15V31 | Execution of higher performance SRAM Cell Using Transmitting Gate |
16V06 | Reduced energy reconfigurable Hilbert transformer design with row skipping multiplier on FPGA |
16V07 | A new energy efficient N-MOS structured 1-bit complete adder |
16V08 | Low strength 8-little bit ALU design using complete adder and multiplexer |
16V09 | A new strength efficient heartbeat activated flip-flop with minimum transistors |
16V10 | Modeling of adders making use of CMOS and GDI reasoning for multiplier applications |
16V11 | Reduced power high speed region efficient error tolerant adder making use of door diffusion insight method |
16V12 | Ultra reduced voltage synthesizable remembrances: a trade-off debate in 65 nm CMOS |
15V15 | Low-Power and Area-Efficient Shift Register Making use of Pulsed Latches |
15V17 | A Low-Power Crossbreed RO PUF With Improved Thermal Stability for Light-weight Programs |
15V19 | Reduced strength Multiplier Architectures making use of Vedic Mathematics in 45 nm Technologies for High Speed Computing |
15V20 | Design amp; Study of a Lower Power Great Speed Full Adder Using GDI Multiplexer |
15V21 | Style of a Power Optimal Reversible FIR Filtration system for Talk Signal Control |
15V23 | Style of Low Power and High Speed Have Select Adder Making use of Brent Kung Adder |
15V32 | Energy and Region Effective Three-Input XOR/XNORs With Systematic Cell Style Methodology |
15V33 | Ultralow-Energy Variation-Aware Style: Adder Structures Research |
15V34 | All Optical Execution of Mach-Zehnder Interferometer based Reversible Sequential Counter tops |
15V35 | Style of Full Adder circuit using Increase Gate MOSFET |
15V36 | Design of Optimized Reversible Binary and BCD Adders |
15V37 | A Single-Ended With Active Feedback Handle 8T Subthreshold SRAM Mobile |
15V38 | Using Boolean Assessments to Improve Detection of Transistor Stuck-open Problems in CMOS Digital Logic Circuits |
15V39 | Modeling CMOS Gates Using Comparable Inverters |
15V40 | Decreasing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm |
15V42 | Variable Latency Risky Han-Carlson Adder |
16V13 | Style of an optimized reversible bidirectional barrel shifter |
16V14 | Encryption using reconfigurable reversible reasoning gate |
16V15 | A 28 nm configurable memory space (TCAM/BCAM/SRAM) using push-rule 6t bit cell allowing logic-in-memory |
16V16 | Style of sign up file making use of reversible logic |
16V17 | A heuristic for linear nearest neighbor conclusion of quantum circuits by SWAP gate insert using -gate look forward |
16V18 | A parallel decimal multiplier using cross binary coded decimal |
15V07 | Execution of Testable Reversible Sequential Routine on FPGA |
15V09 | A Novel Understanding of Reversible LFSR for its Application in Cryptography |
15V11 | IC Layout Style of Decoder Using Electric VLSI Style |
15V12 | Low-Complexity Woods Structures for Getting the First Two Minima |
15V13 | Style of Adiabatic Active Differential Logic for DPA-Resistant Secure Integrated Circuits |
15V14 | Synthesis of Balanced Quaternary Reversible Reasoning Circuit |
16V19 | A customized partial product creator for redundant binary multipliers |
16V20 | A revised partial product power generator for redundant binary multipliers |
16V21 | Pre-encoded multipliers centered on non-redundant radix-4 signed-digit development |
16V22 | Floating-point butterfly architecture centered on binary signed-digit counsel |
16V23 | Low-quantum price circuit buildings for adder and symmetric Boolean features |
16V24 | A high-performance fir filtration system architecture for set and reconfigurable programs |
16V25 | Energy-aware booking of FIR filter structures using a timed automata design |
15V52 | A 32 Little bit MAC Device Design Using Vedic Multiplier and Reversible Logic Gate |
15V53 | Towards reversible QCA computers: reversible entrance and ALU |
15V54 | Style And Development of Efficient Reversible Floating Point Math device |
15V56 | Parallel Prefix Modulo Adder via Double Counsel of Residues in 0, 2 |
15V57 | Style And Execution Of Industry Programmable Door Range Based Error Tolerant Adder For Image Processing Application |
15V58 | Style and Implementation of Arithmetic Logic Unit (ALU) making use of Modified Book Bit Adder in QCA |
15V59 | Quantum Cost Understanding of New Reversible Entrances with Change Based Activity Technique |
15V60 | Style of a Small Reversible Carry Look-Ahead Adder Using Dynamic Development |
16V26 | Design of reversible circuits with higher testability |
16V27 | An improved style of a reversible problem tolerant LUT-based FPGA |
16V28 | FTCAM: An area-efficient flash-based ternary CAM design |
16V29 | Logic synthesis in reversible PLA |
16V30 | Style for testability of sleep convention logic |
16V31 | Synthesis of approximate programmers for on-chip interconnects making use of reversible logic |
16V32 | Fault detection in parity preserving reversible circuits |
15V43 | Index-based Round-Robin Arbiter for NOC Routers |
15V44 | An Enhanced Active Latch Structured Comparator for 8-bit Asynchronous SAR ADC |
15V45 | A Book Ternary Content-Addressable Storage (TCAM) Design Making use of Reversible Reasoning |
15V46 | A book design of reversible 2:4 decoder |
15V47 | Design and Implementation of a Reversible Central Processing Unit |
15V48 | Performance Comparison of Pass Transistor and CMOS Logic Configuration centered De-Multiplexers |
15V50 | Reasoning Debugging of Arithmetic Circuits |
15V51 | Reversible reasoning structured mapping of quaternary sequential circuits using QGFSOP manifestation |
16V33 | Design of reversible circuits with higher testability |
16V34 | Squaring in reversible logic making use of zero crap and decreased ancillary advices |
16V35 | A pre-optimization method to produce preliminary reversible circuits with low quantum price |
16V36 | Ancient elements of reversible logic synthesis |
16V37 | Reversible outlet synthesis making use of binary decision layouts |
16V38 | An effective technique to style a compact reversible programmable logic variety |
16V39 | Re-writing HDL descriptions for line-aware activity of reversible circuits |
16V40 | Exploiting inherent features of reversible circuits for faster combinational equivalence checking |
15V01 | Design of concern encoding centered reversible comparators |
15V02 | On the Analysis of Reversible Sales space�s Multiplier |
15V03 | Berger check and mistake tolerant reversible math component style |
15V04 | Parity Preserving Adder/Subtractor Making use of a Novel Reversible Door |
15V05 | Online Tests for Three Fault Versions in Reversible Circuits |
15V06 | A New Gate for Lower Cost Design of All-optical Reversible Logic Circuit |
WYV62 | Design and Appraisal of hold off, power and region for Parallel prefix adders |
WYV68 | Strategy to design and style a small reversible reduced power binary comparator |
WYV65 | Area�Delay�Power Efficient Carry-Select Adder |
WYV55 | A Lower Power Problem Tolerant Reversible Decoder Making use of MOS Transistor |
WYV61 | Low strength and area efficient carry select adder |
WYV37 | Architectural level power optimisation methods for multipliers |
WYV56 | Style of high speed cross types carry select adder |
WYV57 | Optimized Reversible Vedic Multipliers for High Speed Lower Power procedures |
WYV2 | Radix-8 booth encoded modulo multipliers with adoptive delay for high dynamic variety Residue Number System. |
WYV4 | Style of characterization of parallel pre-fix adders making use of FPGA. |
WYV7 | Decreasing the calculation period in (short bit-width) two�s complement multipliers. |
WYV9 | Structured on radix-2 modified sales space algorithm a fresh VLSI architecture of parallel multiplier accumulator |
WYV36 | The style of high performance clip or barrel integer adder |
WYV54 | A higher velocity binary suspended point multiplier making use of Dadda algorithm |
WYV63 | Detection of hardware Trojan in Ocean using route delay |
WYV66 | Detection of hardware Trojan viruses in Ocean using route delay |
WYV8 | FPGA execution of scalable encryption algorithm |
WYV15 | FPGA implementation of SHA-1 algorithm |
WYV12 | Execution of the hummingbird cryptographic criteria |
WYV35 | Cyclic redundancy check out generation using multiple search for desk algorithms |
WYV1 | FPGA execution of scalable encryption formula |
WYV5 | Self-immunity technique to enhance register file reliability against gentle mistakes |
WYV6 | Design and simulation of UART serial conversation module centered on VHDL |
WYV11 | Equipment implementation of RFID mutual authentication process |
WYV13 | Verilog modeling of WI-FI Macintosh coating for transmitter |
WYV14 | FPGA implementation of USB transceiver macro mobile user interface with usb2.0 specifications |
WYV17 | VHDL execution of lossless information compression |
WYV18 | A VLIW vector press compressor with cascaded SIMD ALU�S |
WYV21 | Design and execution of blue tooth security making use of VHDL |
WYV48 | Design and implementation of APB connection centered on AMBA 4.0 |
WYV50 | Applying CDMA technique to network-on-chip |
WYV22 | Implementation of vending machine controller |
WYV23 | Execution of traffic light control |
WYV24 | Implementation of digital clock |
WYV25 | Implementation of digital voting device controller |
WYV26 | Implementation of common asynchronous recipient/transmitter |
WYV27 | Implementation of serial peripheral interface |
WYV28 | Execution of content addressable storage |
WYV29 | Execution of 32 little bit cyclic redundancy check out |
WYV30 | Implementation of barrel or clip shifter |
WYV31 | Execution of circular robin arbiter |
WYV34 | Limited state machine based vending machine controller with auto-billing functions |
WYV3 | Large throughput da-based DCT with high accuracy error paid out adder forest. |
WYV64 | Parallel multiplier accumulator based on radix-2 revised booth algorithm by using a VLSI architecture |
WYV10 | LUT optimisation for memory-based computation. |
WYV33 | Optimized implementation of FFT processor chip for OFDM techniques |
WYV39 | Arithmetic amp; reasoning device (ALU) style making use of reversible handle |
WYV38 | Style and minimization of reversible circuits for a data buy and storage program |
WYV41 | Style amp; execution of macintosh unit using reversible reasoning |
WYV44 | An effective implementation of suspended point multiplier |
WYV49 | A table-based criteria for pipelined CRC calculation |
WYV69 | Parity protecting logic based fault tolerant reversible ALU |
WYV32 | A novel evaluation of sequential circuits design making use of reversible reasoning gates |
WYV40 | A distinguish between reversible and standard logic gates |
WYV42 | Modified Toffoli door and its applications in designing elements of reversible arithmetic and logic unit |
WYV43 | A fresh reversible design of BCD adder |
WYV45 | Fault tolerant adjustable block carry skip logic (VBCSL) making use of parity preserving |
WYV46 | Style of a nanometric reversible 4-little bit binary table with parallel insert |
WYV47 | Intro to reversible logic gates amp; its application |
WYV51 | Understanding of 2:4 reversible decoder and its programs |
WYV52 | All optical reversible multiplexer design using Mach-Zehnder interferometer |
WYV53 | Style of devoted reversible quantum circuitry for square calculation |
WYV58 | Power efficient code converters using reversible reasoning entrances |
WYV59 | Design of low logical cost conventional reversible adders using story PCTG |
WYV60 | Consideration of synchronous gray code countertop and its options using reversible logic entrance |
WYV67 | An optimized style of binary comparator routine in quantum processing |
WYV70 | ASIC design of reversible multiplier signal |
WYV71 | A reduced power and high efficiency dm^2 adder |
WYV72 | Evaluation and design of a low-voltage low-power double-tail comparator |
WYV73 | Low power heart beat triggered flip-flop style based on indication feed-through scheme |
WYV74 | Raise in read noise margin of single-bit-line SRAM making use of adiabatic switch of word line voltage |
WYV75 | An 8t low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FINFETS |
WYV76 | Low power sound tolerant domino 1-little bit complete adder |
WYV77 | A book low leakage and higher denseness 5t CMOS SRAM cell in 45nmichael technology |
WYV78 | A brand-new style of low power higher speed hybrid CMOS full adder |
WYV79 | A reduced power and high performance dm^2 adder |
WYV80 | A sub-threshold eight transistor (8T) SRAM mobile design for stability improvement |
WYV81 | An arithmetic and logic unit optimized for region and power |
15V61 | Design of high functionality multiply-accumulate calculation device |
15V62 | Efficiency evaluation of a low-power high-speed cross types 1-little bit complete adder routine |
15V63 | An method to style a multiplexer based component of a story reversible door for FPGA architecture |